Along with the recent development in (i) a microfabrication technology, (ii) a technology related to liquid crystal materials, and (iii) a high-density packaging technique, 5 cm through 100 cm diagonal liquid crystal display devices for displaying television images and/or various kinds of images have been distributed in mass quantities on a commercial basis. Such the liquid crystal display device is provided with a liquid crystal panel including two glass substrates, one of which is provided with an RGB colored layer, so that the liquid crystal display device can easily carry out a color display. Further, a so-called active matrix-type liquid crystal panel, which includes a switching element integrated into each pixel, has guaranteed to provide images with less crosstalk, a high response speed, and a high contrast ratio, since it was first commercialized.
The liquid crystal display device (liquid crystal panel) typically includes approximately 200 through 1200 scanning signal lines (gate wires) and approximately 300 through 1600 data signal lines (source wires), the scanning signal lines and the data signal lines being arranged in a matrix. Further, a liquid crystal display device is recently being developed to have a larger screen and a higher resolution, in order to deal with an increasing display capacity.
FIG. 33 is a perspective view illustrating a method disclosed in Patent Literature 7 for mounting a liquid crystal panel. An electric signal is allowed to be supplied to an image display section by a mounting method such as a COG (Chip-On-Glass) method or a TCP (Tape-Carrier-Package) method. According to the COG method, a semiconductor integrated circuit chip 3 for supplying a drive signal is connected with, by an electrically conductive adhesive, an electrode terminal 5 of a scanning signal line formed on one of transparent insulative substrates included in a liquid crystal panel 1, for example, on a glass substrate 2. According to the TCP method, a TCP film 4 which includes, e.g., (i) a base made of a polyimide resin thin film and (ii) a terminal made of copper foil and plated with gold or solder is brought into contact with and fixed to an electrode terminal 6 of a data signal line by a suitable adhesive containing an electrically conductive medium. Here, for convenience of explanation, these two mounting methods are both illustrated in FIG. 33. Actually, however, one of the two mounting methods is selected as needed.
Reference number 7 indicates a wiring path allowing (i) a pixel in an image display section, which is positioned in a substantially center part of the liquid crystal panel 1, and (ii) the electrode terminal 5 of the scanning signal line to be connected with each other, whereas reference number 8 indicates a wiring path allowing (i) a pixel in the image display section and (ii) the electrode terminal 6 of the data signal line to be connected with each other. The wiring paths 7 and 8 are not necessarily made of the same material as that of the electrode terminals 5 and 6. Reference number 9 indicates a counter glass substrate or a color filter substrate. The counter glass substrate or the color filter substrate is the other one of the transparent insulative substrates, and is provided with, on its surface facing the one transparent insulative substrate, a transparent electrically conductive counter electrode, which is common to all liquid crystal cells.
FIG. 34 is an equivalent circuit diagram of an active matrix-type liquid crystal display device including, as a switching element, an insulated gate transistor 10 which is provided for each pixel. In FIG. 34, reference number 11 (in FIG. 33, reference number 7) indicates a scanning signal line, reference number 12 (in FIG. 33, reference number 8) indicates a data signal line, and reference number 13 indicates a liquid crystal cell. Electrically, the liquid crystal cell 13 is regarded as a capacitor element. Elements depicted by full lines are provided on a glass substrate 2, which is one of glass substrates included in a liquid crystal panel 1. A counter electrode 14, which is depicted by broken lines and is common to all liquid crystal cells 13, is formed on a main surface of a glass substrate (color filter substrate) 9, i.e., the other one of the glass substrates, the main surface facing the glass substrate 2. In a case (i) where the insulated gate transistor 10 has a low resistance during off or the liquid crystal cell 13 has a low resistance or (ii) where gradation properties of a display image are regarded as important, the circuit is given an additional feature; for example, an auxiliary storage capacitor (auxiliary capacitor) 15 is additionally provided in parallel with the liquid crystal cell 13, which auxiliary storage capacitor increases a time constant of the liquid crystal cell 13 serving as a load. Reference number 16 indicates a storage capacitor line or a common electrode, which serves as a common bus line for the storage capacitors 15.
FIG. 35 is a cross-sectional view illustrating a main part of an image display section of a liquid crystal display device. As shown in FIG. 35, a liquid crystal panel 1 includes two glass substrates 2 and 9, which are provided so as to be away from each other by a predetermined distance of some μm by a spacer material (not illustrated) such as a resin fiber, a resin bead, or a columnar spacer which is provided on the color filter substrate 9. The clearance (gap) between the glass substrates 2 and 9 is a closed space sealed with a sealing material (not illustrated) which is provided in the periphery of the glass substrate 9 and is made of an organic resin. The closed space is filled with liquid crystal 17.
In order to provide a color display, on a surface of the glass substrate 9 facing the closed space, such an organic thin film (referred to as a “colored layer 18”) is deposited that has a thickness of approximately 1 μm through approximately 2 μm and contains dye and/or pigment. Consequently, a color display function is attained. In this case, the glass substrate 9 is also referred to as a “color filter” (abbreviated as “CF”). Further, depending on the properties of the liquid crystal material 17, an upper surface of the glass substrate 9 and/or a lower surface of the glass substrate 2 is/are provided with a polarizing plate(s) 19, so that the liquid crystal panel 1 serves as an electro-optic element. Currently, most of commercially-available liquid crystal panels employ a TN (twisted nematic) liquid crystal material, and typically require two polarizing plates 19. A transmissive liquid crystal panel includes a backside light source (not illustrated) as a light source, so that white light is emitted from its lower side.
Each of the two grass substrates 2 and 9 is provided with a polyimide resin thin film 20 which is formed so as to be in contact with the liquid crystal 17 and to have a thickness of, e.g., approximately 0.1 μm. The polyimide resin thin film 20 is an alignment film for aligning liquid crystal molecules along a predetermined direction. Reference number 21 indicates a drain electrode (wire) by which (i) a drain of an insulated gate transistor 10 and (ii) a transparent electrically conductive pixel electrode 22 are connected with each other. In many cases, the drain electrode 21 and a data signal line (source wire) 12 are formed concurrently. Provided between the source electrode 12 and the drain electrode 21 is a semiconductor layer 23, which will be described in detail later. In a boundary between colored layers 18 which are adjacent to each other on the color filter substrate 9, there provided a Cr thin film layer 24 having a thickness of approximately 0.1 μm. The Cr thin film layer 24 is a light-shielding member for preventing external light from entering the semiconductor layer 23, the scanning signal line 11, and the data signal line 12. This is an established technique, i.e., a so-called black matrix (abbreviated as “BM”).
In order to manufacture an active matrix substrate 71 including a glass substrate 2 on which a scanning signal line, a data signal line, an insulated gate transistor serving as a switching element, and a pixel electrode are provided, it is indispensable to carry out two or more photolithography (photo-etching) steps each using a photo mask, as well as in a process for manufacturing a semiconductor integrated circuit. However, a step of patterning a semiconductor layer into islands has been streamlined, and a step of forming a contact to the scanning signal line has been eliminated (details thereof are omitted here). In addition, a dry etching technique has been introduced. Thanks to these, the number of necessary photo masks has been now reduced to five, although seven or eight photo masks were necessary before. This greatly contributes to a reduction of a process cost. In order to reduce a manufacturing cost of a liquid crystal display device, it is effective to reduce the process cost in a procedure for manufacturing an active matrix substrate, and it is effective to reduce a cost of components in a panel assembling procedure and a module mounting procedure. These have been commonly-known objects in development. Further, it is clear that reducing the number of manufacturing steps including the photo-etching step would greatly contribute to (i) improvement in productivity in manufacturing of liquid crystal display devices and (ii) a reduction of the cost thereof.
As already described, the typical method for manufacturing the active matrix substrate 71 requires five photo-etching steps. However, Patent Literature 1 discloses a manufacturing method which enables a further reduction of the manufacturing cost. The following will describe a four-mask process disclosed in Patent Literature 1. The four-mask process is a technique for reducing the number of steps or streamlining the steps. Specifically, the four-mask process uses a halftone exposure technique, and carries out, with a single photo mask, (i) a step of patterning a semiconductor layer (including a channel) into islands and (ii) a step of forming a source wire and a drain wire.
Each of FIGS. 36 and 37 shows plan views of one unit of a pixel included in an active matrix substrate 71 to which the four-mask process is applied. Each of FIGS. 38 and 39 shows cross-sectional views illustrating manufacturing steps, viewed in an A-A′ line (i.e., a region of an insulated gate transistor), a B-B′ line (i.e., a region of an electrode terminal of a scanning signal line), and a C-C′ line (i.e., a region of an electrode terminal of a data signal line), each of these lines being shown in (b) of FIG. 37. Conventionally, the insulated gate transistor is often selected from two types, an etch stop type insulated gate transistor and a channel etch type insulated gate transistor. Here, as one example, the channel etch type insulated gate transistor is illustrated.
As shown in (a) of FIG. 36 and (a) of FIG. 38, a glass substrate 2 having a thickness of approximately 0.5 mm through approximately 1.1 mm, for example, “1737” (product name) manufactured by Corning Incorporated, is used as an insulative substrate having high heat resistance, high chemical resistance, and high transparency. First, on one main surface of the glass substrate 2, a first metal layer (i.e., a metal layer for a scanning signal line) having a film thickness of approximately 0.1 μm through approximately 0.3 μm is deposited by use of a vacuum film forming device such as SPT (sputtering). Then, through a microfabrication technology, a scanning signal line 11, which serves also as a gate electrode 11A, and a storage capacitor line 16 are selectively formed. The scanning signal line is made of a material which is determined by comprehensively considering heat resistance, chemical resistance, hydrofluoric acid resistance, and electric conductivity. Typically, the scanning signal line is made of (i) a metal thin film layer made of, e.g., Cr or Ta, each of which has high heat resistance, or (ii) an alloy thin film layer made of, e.g., an MoW alloy.
It is reasonable to use Al (aluminum) as the material of the scanning signal line, in order to reduce a resistance of the scanning signal line and cope with a liquid crystal panel having a larger screen and a higher resolution. However, Al alone has low heat resistance; therefore, currently, the scanning signal line is typically made of a lamination of Al and the above-mentioned heat resistant metal, i.e., Cr, Ta, Mo, or a silicide thereof. Namely, the scanning signal line 11 is typically made of one or more metal layers.
Next, a PCVD (plasma CVD) device is used to sequentially deposit, on an entire surface of the glass substrate 2, three types of thin film layers, i.e., (i) a first silicon nitride (SiNx) layer 30, which becomes a gate insulative layer, (ii) a first amorphous silicon (a-Si) layer 31, which hardly contains an impurity and which becomes a channel of an insulated gate transistor, and (iii) a second amorphous silicon (n+a-Si) layer 33, which contains phosphorus as an impurity and becomes a source and a drain of the insulated gate transistor, so that the first silicon nitride layer 30, the first amorphous silicon layer 31, and the second amorphous silicon layer 33 have film thicknesses of, e.g., approximately 0.3 μm, approximately 0.2 μm, and approximately 0.05 μm, respectively. Subsequently, a vacuum film forming device such as SPT is used to sequentially deposit, e.g., a Ti thin film layer 34 as a heat resistant metal layer having a film thickness of approximately 0.1 μm, an Al thin film layer 35 as a low resistant metal layer having a film thickness of approximately 0.3 μm, and, e.g., a Ti thin film layer 36 as a buffer metal layer having a film thickness of approximately 0.1 μm. Consequently, a material of a source wire and a drain wire is provided.
Then, through a microfabrication technology, (i) a data signal line 12 and (ii) a drain electrode 21 of the insulated gate transistor are selectively formed. The data signal line 12, which serves also as a source electrode of the insulated gate transistor, includes a heat resistant metal layer 34A, a low resistant metal layer 35A, and a buffer metal layer 36A, which are laminated together and partially overlap the gate electrode 11A. Similarly, the drain electrode 21 includes a heat resistant metal layer 34B, a low resistant metal layer 35B, and a buffer metal layer 36B, which are laminated together and partially overlap the gate electrode 11A. In this selective patterning, as shown in (b) of FIG. 36 and (b) of FIG. 38, photosensitive resin patterns 80A and 80B are formed by a halftone exposure technique so that (i) a channel formed region 80B (a hatched region in (b) of FIG. 36) between the source and the drain has a film thickness of, e.g., 1.5 μm and (ii) each of a source wire formed region 80A(12) and a drain wire formed region 80A(21) has a film thickness of 3 μm. This is a significant feature of the streamlined four-mask process.
In order to manufacture the active matrix substrate 71, a positive photosensitive resin is typically used. Therefore, the photosensitive resin patterns 80A and 80B may be formed by use of a photo mask configured as follows: (i) in a part corresponding to the source wire and drain wire formed region 80A, a black region (i.e., a Cr thin film) is provided; (ii) in a part corresponding to the channel formed region 80B, a gray (halftone) region is provided by which an amount of light transmitted through the photo mask is reduced (e.g., a Cr line-and-space pattern having a width of approximately 0.5 μm through approximately 1.5 μm); and (iii) in the other regions, a white region is provided (i.e., the Cr thin film is not provided). Since a resolution of an exposure device is insufficient in the gray region, the line-and-space pattern is not resolved. This allows approximately half of light emitted by a lamp light source toward the photo mask to be transmitted through the gray region. Consequently, it is possible to obtain the photosensitive resin patterns 80A and 80B, having a cross section shaped in a recess as shown in (c) of FIG. 38, according to the property of the positive photosensitive resin leaving as a film. Instead of the slits, the gray region can be made of a metal layer having different film thicknesses or different transmittances, e.g., of a MoSi2 thin film.
As shown in (b) of FIG. 36 and (b) of FIG. 38, by use of the photosensitive resin patterns 80A and 80B as a mask, the Ti thin film layer 36, the Al thin film layer 35, the Ti thin film layer 34, the second amorphous silicon layer 33, and the first amorphous silicon layer 31 are sequentially etched, so that the gate insulative layer 30 is exposed. Thereafter, through ashing means such as oxygen plasma, the thicknesses of the photosensitive resin patterns 80A and 80B are each reduced by 1.5 μm or more. As a result, the photosensitive resin pattern 80B disappears, so that a part of the Ti thin film layer 36 which part is in the channel formed region is exposed (not illustrated). This allows, as shown in (c) of FIG. 36 and (c) of FIG. 38, photosensitive resin patterns 80C(12) and 80C(21), each of which has a reduced thickness, to be left only in the source wire formed region and the drain wire formed region.
By use of the photosensitive resin patterns 80C(12) and 80C(21), each of which has a reduced film thickness, etching is carried out in a region between the source wire and the drain wire (i.e., the channel formed region). Namely, in this region, the Ti thin film layer 36, the Al thin film layer 35, the Ti thin film layer 34, the second amorphous silicon layer 33, and the first amorphous silicon layer 31 are sequentially etched again, so that the first amorphous silicon layer 31A is left to have a thickness of approximately 0.05 μm through approximately 0.1 μm. At this time, a source 33S and a drain 33D, each of which is made of the second amorphous silicon layer, are separated from each other. Thus, the source wire 12 and the drain wire 21 are formed in such a manner that, after the metal layer is etched, the first amorphous silicon layer 31A is etched so as to be left to have a thickness of approximately 0.05 μm through 0.1 μm. On this account, an insulated gate transistor obtained by such the manufacturing method is called a “channel etch type transistor”.
In the above oxygen plasma process, the photosensitive resin pattern 80A is transformed into the photosensitive resin pattern 80C, which has a reduced film thickness. Therefore, in order to suppress a variation in the pattern size, it is preferable to strengthen anisotropy. Concretely, the oxygen plasma process is preferably carried out by RIE (Reactive Ion Etching) method, further preferably by ICP (Inductive Coupled Plasma) method or TCP (Transfer Coupled Plasma) method, each involving a high-density plasma source.
The photosensitive resin patterns 80C(12) and 80C(21) are removed. Thereafter, on the entire surface of the glass substrate 2, a second SiNx layer having a film thickness of approximately 0.3 μm is deposited as a transparent insulative layer, so that a passivation insulative layer 37 is formed. Subsequently, as shown in (a) of FIG. 37 and (a) of FIG. 39, (i) an opening 62 is formed above the drain electrode 21, (ii) an opening 63 is formed in a region which is outside the image display section and in which an electrode terminal of the scanning signal line 11 is to be formed, and (iii) an opening 64 is formed in a region which is outside the image display section and in which an electrode terminal of the data signal line 12 is to be formed. A part of the passivation insulative layer 37 and a part of the gate insulative layer 30 which parts correspond to the opening 63 are removed, so as to expose, in the opening 63, a part 5 of the scanning signal line. Further, parts of the passivation insulative layer 37 which parts respectively correspond to the openings 62 and 64 are removed, so as to expose a part of the drain electrode 21 and a part 6 of the data signal line. Similarly, an opening 65 is formed above the storage capacitor line 16, so as to expose a part of the storage capacitor line 16.
Lastly, a vacuum film forming device such as SPT is used to deposit a transparent electrically conductive layer having a film thickness of approximately 0.1 μm through approximately 0.2 μm, e.g., ITO (Indium-Tin-Oxide), IZO (Indium-Zinc-Oxide), or a mixed crystal thereof. Then, as shown in (b) of FIG. 37 and (b) of FIG. 39, a pixel electrode 22, which is transparent and electrically conductive, is selectively formed on the passivation insulative layer 37 by a microfabrication technology so as to include the opening 62. Thus, the active matrix substrate 71 is completed. Now, a configuration of a storage capacitor 15 (FIG. 34) is explained. As shown in (b) of FIG. 37 and (b) of FIG. 39, the storage capacitor 15 is configured by the drain electrode 21 and the storage capacitor line 16 overlapping each other via the gate insulative layer 30, the first amorphous silicon layer 31A, and the second amorphous silicon layer 33D, when seen in a plan view (see a region 50 hatched with lines sloping from left to right in (a) of FIG. 37). Further, speaking of electrode terminals, electrode terminals 5A and 6A, each of which is transparent and electrically conductive, are selectively formed on the passivation insulative layer 37 so as to include the openings 63 and 64, respectively.
As described above, in order to use Al to make the source wire 12 and the drain wire 21, each of the source wire 12 and the drain wire 21 needs the heat resistant layer 34 for securing electrical connection with the second amorphous silicon 33. Furthermore, the buffer metal layer 36 needs to be provided between (i) the source wire 12 and the drain wire 21 and (ii) the transparent electrically conductive layer, in order to prevent them from working as a battery in an alkaline fluid. On this account, each of the source and drain wires must be formed to have a three-layer configuration. However, in a liquid crystal panel having a large screen or a high resolution, it is difficult to avoid use of the low resistance metal layer (Al thin film layer), since resistances of the source and drain wires must be strictly limited in such the liquid crystal panel.
Conventionally, in a case where the heat resistant metal layer 34 and the buffer metal layer 36 are made of Ti, etching of such the heat resistant metal layer 34 and buffer metal layer 36 need be carried out by a dry etching process with a chlorine gas, and accordingly etching of Al also needs to be carried out by dry etching process with a chlorine gas. This costs high not only in terms of materials but also in terms of production equipment. Recently, however, a new chemical for etching Ti is provided by Mitsubishi Chemical Corporation, and this will probably reduce the cost of the production equipment. In a case where the heat resistant metal layer 34 and the buffer metal layer 36 are made of Mo instead of Ti, it is commonly carried out to etch a three-layer structure of Mo/Al/Mo by a single chemical treatment with a phosphoric acid solution containing an appropriate amount of nitric acid. It is easily understood that this will reduce investment in production equipment. Further, needless to say, efforts have been made to simplify the source and drain wires as much as possible, in order to reduce the production cost.
The channel forming step employed in the four-mask process concurrently removes (i) a part of the material of the source wire and the drain wire and (ii) a part of the semiconductor layer containing an impurity, both of the parts being located between the source wire 12 and the drain wire 21. Therefore, this channel forming step determines a channel length (4 μm through 6 μm in current mass-produced products), which greatly affects characteristics of the insulated gate transistor during on. Since a variation in the channel length significantly changes an electric current value of the insulated gate transistor during on, strict manufacturing control is typically requested therefor.
However, the channel length, i.e., the pattern size of the halftone exposure region is affected by a lot of parameters such as: an amount of exposure (a strength of a light source and patterning accuracy of a photo mask, particularly, sizes of lines and spaces); a thickness of a photosensitive resin applied; a development process condition of the photosensitive resin; and/or how much a film thickness of the photosensitive resin is reduced in the etching step. Furthermore, since it is also necessary to consider uniformity of these parameters in the surface, a display panel substrate having a target channel length cannot be always produced with a high yield and in a stable manner.
On this account, in a case of using the above-described channel forming step employed in the four-mask process, more strict manufacturing control than conventional manufacturing control is necessary. Thus, the four-mask process has not been completed at a high level. Particularly in a case where the channel length is 5 μm or less, as the thicknesses of the photosensitive resin patterns 80A(12) and 80A(21) reduce, an effect of the pattern size becomes greater. Thus, in this case, the above tendency is significant.
It is relatively easy to prepare a photo mask so as to have a large size in advance, in order to prevent a reduction of the pattern size, which occurs along with a reduction of the film thickness of the photosensitive resin pattern. However, the pattern size of the photosensitive resin 80B, which is for the channel region, cannot be made smaller than a resolution limit (approximately 3 μm at minimum) of the exposure device. Therefore, after all, the channel length is longer twice an amount of a reduction of the photosensitive resin pattern which reduction is observed along a horizontal direction. Furthermore, a variation in the amount of the reduction of the photosensitive resin pattern also becomes greater in the surface of the glass substrate. This is considered to be one of the reasons why the four-mask process is slow to be introduced in existing production lines for a glass substrate of 1 m or more.